View LTC3701EGN_915720.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ltc3701 3701fa applicatio s u features descriptio u typical applicatio u 2-phase, low input voltage, dual step-down dc/dc controller the ltc ? 3701 is a 2-phase dual constant frequency cur- rent mode step-down dc/dc controller providing excellent load and line regulation. power loss and noise due to esr of the input capacitor are minimized by operating the two controller output stages out-of-phase. the ltc3701 provides a 0.8v 2% voltage reference and consumes only 460 m a of quiescent current. to further maximize the life of a battery source, the external p-channel mosfet is turned on continuously in dropout (100% duty cycle). switching frequency is internally set at 550khz, allowing the use of small inductors and capacitors. for noise sen- sitive applications, the ltc3701 can be externally syn- chronized using its phase-locked loop. the frequency can also be externally set from 300khz to 750khz by applying a voltage to the plllpf pin. burst mode operation is inhib- ited during synchronization or when the extclk/mode pin is pulled low to reduce noise and rf interference. the ltc3701 contains independent internal soft-start circuitry for each controller. other features include a power good output voltage monitor and output overvolt- age and short-circuit protection. the ltc3701 is available in a small footprint 16-lead nar- row ssop package. n out-of-phase controllers reduce required input capacitance n true pll for frequency locking or frequency adjustment n operating frequency range: 300khz to 750khz n wide v in range: 2.5v to 10v n constant frequency current mode architecture n low dropout: 100% duty cycle n power good output voltage monitor n internal soft-start circuitry n selectable burst mode ? /pulse skipping operation at light loads n output overvoltage protection n low quiescent current: 460 m a n 0.8v 2% voltage reference n small 16-lead narrow ssop package n one or two lithium-ion powered applications n notebook and handheld computers n personal digital assistants n portable instruments n distributed dc power systems figure 1. high efficiency 2-phase 550khz dual step-down converter efficiency vs load current + + sense1 v fb1 i th /run1 sgnd i th /run2 v fb2 plllpf sense2 sense1 + v in pgate1 pgnd pgate2 pgood extclk/mode sense2 + 1 3 2 4 6 5 7 8 16 15 14 13 12 11 10 9 ltc3701 220pf 220pf 10k 10k d1, d2: ir10bq015 l1, l2: lqn6c-4r7 m1, m2: fdc638p 78.7k 80.6k 100k 169k l1 4.7 h 47 f 10 f 47 f 0.03 0.03 l2 4.7 h d1 m1 m2 d2 3701 f01a v out1 2.5v 2a v in 2.5v to 9.8v v out2 1.8v 2a , ltc and lt are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. load current (ma) 60 efficiency (%) 80 100 50 70 90 1 100 1000 10000 3701 f01b 40 10 v in = 3.3v v in = 8.4v v out = 2.5v v in = 4.2v v in = 6v
2 ltc3701 3701fa (note 1) input supply voltage (v in )........................ C 0.3v to 10v sense1 C , sense2 C , pgate1, pgate2, plllpf, sense1 + , sense2 + , extclk/mode voltages .............. C 0.3v to (v in + 0.3v) v fb1 , v fb2 , i th /run1, i th /run2 voltages .................................. C 0.3v to 2.4v pgood voltage ........................................ C 0.3v to 10v pgate1, pgate2 peak output current (<10 m s) ....... 1a operating ambient temperature range (note 2) ...................................................C40 c to 85 c storage ambient temperature range ... C 65 c to 150 c junction temperature (note 3) ............................ 125 c lead temperature (soldering, 10 sec).................. 300 c the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 4.2v unless otherwise noted. absolute axi u rati gs w ww u package/order i for atio uu w order part number LTC3701EGN electrical characteristics t jmax = 150 c, q ja = 140 c/w gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 sense1 i th /run1 v fb1 sgnd v fb2 i th /run2 plllpf sense2 sense1 + v in pgate1 pgnd pgate2 pgood extclk/mode sense2 + parameter conditions min typ max units main control loops input dc supply current (note 4) normal operation 2.5v < v in < 9.8v 460 780 m a sleep mode 2.5v < v in < 9.8v 305 470 m a shutdown 2.5v < v in < 9.8v, i th /run1 = i th /run2 = 0v 9 28 m a uvlo v in < uvlo threshold 18 30 m a undervoltage lockout threshold v in falling l 1.55 2.00 2.50 v v in rising 1.70 2.12 2.55 v shutdown threshold at i th /run1, 2 0.2 0.35 0.5 v start-up current source on i th /run1, 2 v ith /run1, 2 = 0v 0.25 0.5 0.85 m a regulated feedback voltage 0 c to 70 c (note 5), i th /run = 1.3v l 0.784 0.8 0.816 v C40 c to 85 c (note 5) l 0.774 0.8 0.826 v output voltage line regulation 2.5v < v in < 9.8v (note 5) 0.05 0.20 mv/v output voltage load regulation i th /run = 0.9v (note 5) 0.2 0.8 % i th /run = 1.6v C 0.2 C 0.8 % v fb1, 2 input current (note 5) 10 50 na output overvoltage protect threshold measured at v fb 0.835 0.88 0.930 v output overvoltage protect hysteresis 20 mv gate drive 1, 2 rise time c l = 3000pf 40 ns gate drive 1, 2 fall time c l = 3000pf 40 ns maximum current sense voltage (sense + C sense C ) (note 6) 95 120 145 mv soft-start current sense voltage step 30 mv time to maximum sense voltage 2048 cycles gn part marking 3701 consult ltc marketing for parts specified with wider operating temperature ranges.
3 ltc3701 3701fa the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 4.2v unless otherwise noted. electrical characteristics parameter conditions min typ max units oscillator and phase-locked loop oscillator frequency v plllpf = 1.2v or floating 500 550 600 khz v plllpf = 0v 230 280 320 khz v plllpf 3 2.4v 690 775 890 khz phase detector output current sinking f extclk/mode < f osc C5 m a sourcing f extclk/mode > f osc 5 m a pgood output pgood voltage low i pgood = 500 m a 70 150 mv pgood trip level v fb with respect to set output voltage v fb ramping positive C15 C8 C2.5 % v fb ramping negative 2.5 8 15 % note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc3701e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: tj is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? q ja c/w) note 4: dynamic supply current is higher due to gate charge being delivered at the switching frequency. note 5: the ltc3701 is tested in a feedback loop that servos i th/run to a specified voltage and measures the resultant v fb voltage. note 6: peak current sense voltage is reduced dependent on duty cycle to a percentage of value as given in figure 2. typical perfor a ce characteristics uw reference voltage vs temperature temperature ( c) ?0 reference voltage (v) 0.795 0.800 0.805 60 3701 g01 0.790 0.785 ?0 20 ?0 80 0 40 100 0.780 0.775 0.810 v in = 4.2v temperature ( c) ?0 i th /run voltage (v) 0.38 0.44 0.50 0 40 100 3701 g02 0.32 0.26 0.36 0.42 0.48 0.30 0.24 0.34 0.40 0.46 0.28 0.22 0.20 ?0 20 20 60 80 v in = 4.2v temperature ( c) ?0 0 frequency (khz) 100 300 400 500 1000 700 ?0 20 40 3701 g03 200 800 900 600 ?0 0 60 80 100 v in = 4.2v plllpf = 2.4v plllpf = 0v plllpf = float shutdown threshold vs temperature oscillator frequency vs temperature
4 ltc3701 3701fa typical perfor a ce characteristics uw undervoltage lockout trip voltage (falling) vs temperature temperature ( c) ?0 1.85 input voltage (v) 1.90 1.95 2.00 2.05 ?0 20 60 100 3701 g04 2.10 2.15 ?0 0 40 80 undervoltage lockout trip voltage (rising) vs temperature temperature ( c) ?0 2.00 input voltage (v) 2.02 2.06 2.08 2.10 2.20 2.14 ?0 20 40 3701 g05 2.04 2.16 2.18 2.12 ?0 0 60 80 100 maximum current sense threshold vs temperature input and shutdown currents vs input voltage efficiency vs load current (pulse skipping mode) pgood r on vs input voltage 2-phase operation temperature ( c) ?0 maximum current sense threshold (mv) 125 120 115 110 105 100 0 40 100 3701 g06 ?0 ?0 20 60 80 input voltage (v) 2 input current ( a) 4 6 711 3701 g07 35 8 9 10 600 500 400 300 200 100 0 pulse skipping mode operation (extclk/mode = 0v) burst mode operation (extclk/mode = v in ) shutdown (i th /run 1,2 = 0v) figure 1 circuit load current = 0a load current (ma) efficiency (%) 100 90 80 70 60 50 40 1 100 100o 1oooo 3701 g08 10 figure 1 circuit extclk/mode = gnd v out = 2.5v v in = 3.3v v in = 4.2v v in = 6v v in = 8.4v input voltage (v) 500 450 400 350 300 250 200 150 100 50 0 pgood r ds(on) ( ) 3701 g09 0123 4 5 67 8910 i pgood = 500 a sw1 5v/div sw2 5v/div input current 1a/div figure 1 circuit 500ns/div
5 ltc3701 3701fa uu u pi fu ctio s sense1 C , sense2 C (pins 1, 8): the (C) inputs to the differential current comparators. i th /run1, i th /run2 (pins 2, 6): these pins each serve two functions. each pin serves as the error amplifier compensation point as well as the run control input for the respective controller. forcing one pin below 0.35v causes the functions associated with that controller to be shut down. forcing both i th/run pins below 0.35v causes the device to be shut down. nominal operating voltage range on these pins is from 0.7v to 1.9v. v fb1 , v fb2 (pins 3, 5): each receives the remotely sensed feedback voltage for each controller from an external resistive divider across the output. sgnd (pin 4): signal ground. plllpf (pin 7): serves as the lowpass filter point for the pll and as the voltage control input to the internal oscillator. normally, a series rc is connected between this pin and ground when synchronizing to an external clock. nominal voltage range is from 0v to 2.4v. frequency can be set by forcing this pin with a voltage. tying this pin to gnd selects 300khz. tying to v in or a voltage 3 2.4v selects 750khz. floating this pin selects 550khz opera- tion. sense2 + (pv in2 ), sense1 + (pv in1 ) (pins 9, 16): the (+) inputs to the differential current comparators. these pins also power the gate drivers. extclk/mode (pin 10): external clock input. applying a clock to this pin causes the internal oscillator to phase- lock to the external clock (nominal lock frequency range between 300khz and 750khz). this also disables burst mode operation but allows pulse-skipping at low load currents. forcing this pin high enables burst mode operation. forcing this pin low enables pulse-skipping mode. in these cases, the frequency of the internal oscillator is set by the voltage on the plllpf pin. if the plllpf voltage is not set externally, the frequency internally defaults to 550khz. pgood (pin 11): power good output voltage monitor open-drain logic output. this pin is pulled to ground when the voltage on either feedback pin (v fb1 , v fb2 ) is not within 8% of its nominal set point. pgood is pulled low when channel 1 or both channels are shut down. when channel 2 is shut down and channel 1 enabled, the pgood output indicates the state of v fb1 only. pgate2, pgate1 (pins 12, 14): gate drivers for the external p-channel mosfets. these pins swing from 0 to sense + (pv in ). pgnd (pin 13): ground pin for gate drivers. v in (pin 15): chip signal power supply input. this pin powers the entire chip except for the gate drivers.
6 ltc3701 3701fa fu ctio al diagra u u w 14 13 pgate1 pgnd 0.880v 0.3v r1 v fb1 i th /run1 v in v in i th clamp shdn1 ov1 pgood1 duplicate for second channel v ref 0.8v 0.35v 0.74v 3701 bd pv in1 ov1 sleep1 sc1 0.5 a + + + + + 3 2 switching logic and blanking circuit eamp + + + 0.15v clk1 burstdis 0.3v q clk1 slope1 sense1 m1 d1 l1 r sense1 s r sense1 + v in c in v in 15 i cmp voltage controlled oscillator undervoltage lockout voltage reference clk1 slope1 burstdis slope2 pgood1 pgood2 shdn2 shdn1 clk2 soft-start slope comp phase detector 10 7 extclk/mode plllpf 10k v in pgood 100 uv shdn2 shdn1 uvsd v ref 0.8v 11 sgnd 4 clock detect burst defeat ovp scp r c r2 c out v out c c 1 16 r c c c
7 ltc3701 3701fa operatio u main control loop the ltc3701 uses a constant frequency, current mode architecture with the two controller channels operating 180 degrees out of phase. during normal operation, each external p-channel power mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the current comparator (i cmp ) resets the latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th /run pin, which is the output of each error amplifier, eamp. the v fb pin receives the voltage feedback signal, which is compared to the internal reference voltage by the eamp. when the load current increases, it causes a slight decrease in v fb relative to the 0.8v reference, which in turn, causes the i th / run voltage to increase until the average inductor current matches the new load current. each main control loop is shut down by pulling the respective i th /run pin low. when both i th /run1 and i th / run2 are low, all ltc3701 controller functions are shut down. releasing i th /run allows an internal 0.5 m a current source to charge up the external compensation network. when the i th /run pin reaches 0.35v, the main control loop is enabled with the i th /run voltage then pulled up to its zero current level of approximately 0.7v. after the loop is enabled, an internal soft-start begins. during this soft- start time of 2048 clock cycles, the i th /run voltage is clamped such that the maximum peak current sense voltage (v sense + C v sense C ) is held to approximately 0%, 25%, 50% and 75%, respectively, of its maximum value of 120mv for four equally timed intervals. after soft-start is completed, full current operation is allowed. as the exter- nal compensation network continues to charge, the corre- sponding output current trip level follows, allowing normal operation. comparator ovp guards against transient output voltage overshoots greater than 10% by turning off the external p-channel power mosfet and keeping it off until the fault is removed. burst mode operation the ltc3701 can be enabled to enter burst mode opera- tion at low load currents by tying the extclk/mode pin to (refer to functional diagram) v in or to a voltage of at least 2v. to disable burst mode operation and enable pwm pulse skipping mode, connect the extclk/mode pin to ground. in this mode, the efficiency is lower at light loads. however, pulse skipping mode has the advantages of lower output ripple and less interference to audio circuitry. when a controller is in burst mode operation, the peak current of the inductor is set as if v ith /run = 1v, even though the voltage at the i th /run pin is at a lower value. if the inductors average current is greater than the load requirement, the voltage at the i th /run pin will drop. when the i th /run voltage goes below 0.85v, the sleep signal goes high, turning off the external mosfet. the sleep signal goes low when the i th /run voltage goes above 0.925v and that controller channel resumes normal operation. the next oscillator cycle will turn the external mosfet on and the switching cycle repeats. frequency synchronization a phase-locked loop (pll) is available on the ltc3701 to allow the internal oscillator to be synchronized to an external clock source connected to the extclk/mode pin. the output of the phase detector at the plllpf pin operates over a 0v to 2.4v range corresponding to ap- proximately 300khz to 750khz. when locked, the pll aligns the turn-on of the external mosfet of controller channel 1 to the rising edge of the synchronizing signal. the turn-on of the external mosfet of controller channel 2 is 180 degrees out of phase with the rising edge of the external clock source. when the ltc3701 is clocked by an external source, burst mode operation is disabled and the ltc3701 operates in pwm pulse skipping mode. in this mode, when the output load is very low, the current comparator i cmp may remain tripped for several cycles and force the external mosfet to stay off for the same number of cycles. increasing the output load slightly allows constant frequency pwm op- eration to resume. this mode exhibits low output ripple as well as low audio noise and reduced rf interference while providing reasonable low current efficiency.
8 ltc3701 3701fa dropout operation when the input supply voltage decreases towards the output voltage, the rate of change of the inductor current during the on cycle decreases. this reduction means that the external p-channel mosfet will remain on for more than one oscillator cycle if the inductor current has not ramped up to the threshold set by eamp on the i th /run pin. further reduction in input supply voltage will eventu- ally cause the p-channel mosfet to be turned on 100%, i.e., dc. the output voltage will then be determined by the input voltage minus the voltage drop across the mosfet, the sense resistor and the inductor. undervoltage lockout to prevent operation of the p-channel mosfet below safe input voltage levels, an undervoltage lockout is incorpo- rated into the ltc3701. when the input supply voltage drops below 2v, the p-channel mosfet and all circuitry are turned off except the undervoltage block, which draws only several microamperes. short-circuit protection when an output is shorted to ground (v fb < 0.3v), the switching frequency of that channel is reduced to 1/5 of the normal operating frequency. the other controller channel is unaffected and maintains normal operation. this lower frequency allows the inductor current to safely discharge, thereby preventing current runaway. the switch- ing frequency will return to its normal value when the feedback voltage rises above 0.3v. during the first 64 cycles (nonzero-current cycles) of soft-start, however, the controller operates at its full frequency. output overvoltage protection as a further protection, the overvoltage comparator in the ltc3701 will turn the external mosfet off when the feedback voltage has risen 10% above the reference voltage of 0.8v. this comparator has a typical hysteresis of 20mv. slope compensation and peak inductor current the inductors peak current is determined by: i vv r pk ith run sense = / . 07 10 when the ltc3701 is operating below 20% duty cycle. however, once the duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak inductor current. the amount of reduction is given by the curve in figure 2. operatio u (refer to functional diagram) figure 2. maximum peak current vs duty cycle duty cycle (%) 10 sf = i/i max (%) 60 80 110 100 90 3701 f02 40 20 50 70 90 30 10 0 30 50 70 20 0 40 60 80 100 power good (pgood) pin a window comparator monitors both output voltages and the open-drain pgood output is pulled low when the divided down output voltages are not within 8% of the reference voltage of 0.8v. pgood is pulled low when channel 1 or both channels are shut down. when chan- nel 2 is shut down and channel 1 enabled, the pgood output indicates the state of channel 1 only. 2-phase operation the ltc3701 dual switching controller offers the consid- erable benefits of using 2-phase operation. circuit ben- efits include lower input filtering requirements, reduced electromagnetic interference (emi) and increased effi- ciency associated with 2-phase operation.
9 ltc3701 3701fa single phase dual controller 2-phase dual controller sw1 (v) sw2 (v) i l1 i l2 i in 3701 f03 figure 3. example waveforms for a single switching regulator channel vs 2-phase ltc3701 system with both channels switching operatio u (refer to functional diagram) input voltage (v) 2 0 input capacitor rms current 0.2 0.6 0.8 1.0 2.0 1.4 4 6 7 3701 f04 0.4 1.6 1.8 1.2 35 8 9 10 single phase dual controler 2-phase dual controler v out1 = 2.5v/2a v out2 = 1.8v/2a figure 4. rms input current comparison why the need for 2-phase operation? until recently, con- stant frequency dual switching regulators operated both channels in phase (i.e., single phase operation). this means that both topside mosfets are turned on at the same time, causing current pulses of up to twice the amplitude of those from a single regulator to be drawn from the input capacitor. these large amplitude pulses increase the total rms current flowing into the input capacitor, requiring the use of more expensive input capacitors, and increasing both emi and losses in the input capacitor and input power supply. with 2-phase operation, the two channels of the ltc3701 are operated 180 degrees out of phase. this effectively interleaves the current pulses coming from the switches, greatly reducing the overlap time where they add together. the result is a significant reduction in the total rms input current, which in turn allows for use of less expensive input capacitors, reduces shielding requirements for emi and improves real world operating efficiency. figure 3 shows example waveforms for a single switching regulator channel versus a 2-phase ltc3701 system with both channels switching. a single phase dual regulator system with both sides switching would exhibit twice the single side numbers. in this example, 2-phase operation reduced the rms input current from 1.79a rms to 0.91a rms . while this is an impressive reduction in itself, remember that power losses are proportional to i rms 2 , meaning that actual power wasted is reduced by a factor of 3.86. the reduced input ripple current also means that less power is lost in the input power path, which could include batteries, switches, trace/connector resistances, and protection circuitry. improvements in both conducted and radiated emi also directly accrue as a result of the reduced rms input current and voltage. of course, the improvement afforded by 2-phase opera- tion is a function of the dual switching regulators relative duty cycles, which in turn are dependent upon the input voltage v in . figure 4 shows how the rms input current varies for 1-phase and 2-phase operation for 2.5v and 1.8v regulators over a wide input voltage range. it can be readily seen that the advantages of 2-phase operation are not limited to a narrow operating range, but in fact extend over a wide region. a good rule of thumb for most applications is that 2-phase operation will reduce the input capacitor requirement to that for just one channel operating at maximum current and 50% duty cycle.
10 ltc3701 3701fa applicatio s i for atio wu uu the basic ltc3701 application circuit is shown in fig- ure 1. external component selection is driven by the load requirement and begins with the selection of l and r sense . next, the power mosfet m1 and the output diode d1 are selected. finally c in (c1) and c out (c2) are chosen. r sense selection for output current r sense is chosen based on the required output current. since the current comparator monitors the voltage devel- oped across r sense , the threshold of the comparator determines the inductors peak current. the output cur- rent that the ltc3701 can provide is given by: i r i out sense ripple = 0 095 2 . where i ripple is the inductor peak-to-peak ripple current (see inductor value calculation). a reasonable starting point for setting ripple current is i ripple = (0.4)(i out ). rearranging the above equation yields: r i sense out = 1 12 7 . for duty cycle < 20% however, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of r sense to provide the required amount of current. using figure 2, the value of r sense is: r sf i sense out = ()()() 12 7 100 . for noise sensitive applications, a 1nf capacitor placed between the sense + and sense C pins very close to the chip is suggested. inductor value calculation the inductor selection will depend on the operating fre- quency of the ltc3701. the internal nominal frequency is 550khz, but can be externally synchronized or set from approximately 300khz to 750khz. the operating frequency and inductor selection are inter- related in that higher frequencies permit the use of a kool m m is a registered trademark of magnetics, inc. smaller inductor for the same amount of inductor ripple current. however, this is at the expense of efficiency due to an increase in mosfet gate charge and switching losses. the inductance value also has a direct effect on ripple current. the ripple current, i ripple , decreases with higher inductance or frequency. the inductors peak-to-peak ripple current is: i vv fl vv vv ripple in out out d in d = + + ? ? ? ? where f is the operating frequency and v d is the forward voltage drop of the external schottky diode. accepting larger values of i ripple allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple cur- rent is i ripple = 0.4(i out(max) ). the maximum i ripple occurs at the maximum input voltage. with burst mode operation selected on the ltc3701, the ripple current is normally set such that the inductor current is continuous during the burst periods. therefore, the peak-to-peak ripple current must not exceed: i ripple (0.03)/r sense this implies a minimum inductance of: l vv f r vv vv v min in out sense out d in d in max = ? ? ? ? + + ? ? ? ? = () . () 003 use v in a smaller value than l min could be used in the circuit, however, the inductor current will not be continuous during burst periods. inductor core selection once the value of l is known, the type of inductor must be selected. high efficiency converters generally cannot af- ford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m m ? cores. actual core loss is independent of core
11 ltc3701 3701fa size for a fixed inductor value, but is very dependent on the inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will in- crease. ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design cur- rent is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! molypermalloy (from magnetics, inc.) is a very good, low loss core material for toroids, but is more expensive than ferrite. a reasonable compromise from the same manu- facturer is kool m m . toroids are very space efficient, especially when several layers of wire can be used, while inductors wound on bobbins are generally easier to sur- face mount. however, new designs for surface mount that do not increase the height significantly are available from coiltronics, coilcraft, dale and sumida. power mosfet selection an external p-channel mosfet must be selected for use with each channel of the ltc3701. the main selection criteria for the power mosfet are the threshold voltage v gs(th) , on resistance r ds(on) , reverse transfer capaci- tance c rss and the total gate charge. since the ltc3701 is designed for operation down to low input voltages, a sublogic level threshold mosfet (r ds(on) guaranteed at v gs = 2.5v) is required for applications that work close to this voltage. when these mosfets are used, make sure that the input supply to the ltc3701 is less than the absolute maximum mosfet v gs rating, typically 8v. the required minimum r ds(on) of the mosfet is gov- erned by its allowable power dissipation. for applications that may operate the ltc3701 in dropout, i.e., 100% duty cycle, the required r ds(on) is given by: r p ip ds on dc p out max () % () = = () + () 100 2 1 d where p p is the allowable power dissipation and d p is the temperature dependency of r ds(on) . (1 + d p) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d p = 0.005/ c can be used as an approximation for low voltage mosfets. in applications where the maximum duty cycle is less than 100% and the ltc3701 is in continuous mode, the r ds(on) is governed by: r p dc i p ds on p out () @ () + () 2 1 d where dc is the maximum operating duty cycle for that channel of the ltc3701. output diode selection the catch diode carries load current during the switch off- time. the average diode current is therefore dependent on the p-channel mosfet duty cycle. at high input voltages, the diode conducts most of the time. as v in approaches v out , the diode conducts for only a small fraction of the time. the most stressful condition for the diode is when the output is short-circuited. under this condition, the diode must safely handle i peak at close to 100% duty cycle. therefore, it is important to adequately specify the diode peak current and average power dissipation so as not to exceed the diodes ratings. under normal load conditions, the average current con- ducted by the diode is: i vv vv i d in out in d out = + ? ? ? ? the allowable forward voltage drop in the diode is calcu- lated from the maximum short-circuit current as: v p i f d peak ? where p d is the allowable power dissipation and will be determined by efficiency and/or thermal requirements. a schottky diode is a good choice for low forward drop and fast switching time. remember to keep lead length short and observe proper grounding (see board layout check- list) to avoid ringing and increased dissipation. applicatio s i for atio wu uu
12 ltc3701 3701fa c in and c out selection the selection of c in is simplified by the 2-phase architec- ture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the control- ler with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms capacitor current requirement. increasing the output cur- rent drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the p-channel mosfet is a square wave of duty cycle (v out + v d )/ (v in + v d ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c i vv vvvv in max in d out d in out required i rms ? + + ()( ) [] / 12 this formula has a maximum at v in = 2v out + v d , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufactur- ers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3701, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the benefit of the ltc3701 2-phase operation can be cal- culated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse re- sistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2-phase system. the overall benefit of a multiphase design will only be fully realized when the source imped- ance of the power supply/battery is included in the effi- ciency testing. the sources of the p-channel mosfets should be placed within 1cm of each other and share a common c in (s). separating the sources and c in may pro- duce undesirable voltage and current resonances at v in . a small (0.1 m f to 1 m f) bypass capacitor between the chip v in pin and ground, placed close to the ltc3701, is also suggested. a 10 w resistor placed between c in (c1) and the v in pin provides further isolation between the two channels. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple ( d v out ) is approximated by: d? + ? ? ? ? v i esr fc out ripple out 1 8 where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. low supply operation although the ltc3701 can function down to approximately 2v, the maximum allowable output current is reduced when v in decreases below 3v. figure 5 shows the amount of change as the supply is reduced down to 2v. also shown is the effect of v in on v ref as v in goes below 2.3v. setting output voltage the ltc3701 output voltages are each set by an external feedback resistive divider carefully placed across the output capacitor (see figure 6). the resultant feedback signal is compared with an internal 0.8v reference by the applicatio s i for atio wu uu
13 ltc3701 3701fa applicatio s i for atio wu uu error amplifier. the regulated output voltage is deter- mined by: vv r r out =+ ? ? ? ? 08 1 2 1 . for most applications, an 80k resistor is suggested for r1. to prevent stray pickup, a 100pf capacitor is suggested across r1 close to the ltc3701. the output of the phase detector is a pair of complemen- tary current sources that charge or discharge the external filter network connected to the plllpf pin. the relation- ship between the voltage on the plllpf pin and operating frequency is shown in figure 7 and specified in the electrical characteristics table. note that the ltc3701 can only be synchronized to an external clock whose fre- quency is within the frequency range of the ltc3701s internal oscillator, which is specified in the electrical characteristics table. a simplified block diagram of the pll is shown in figure 8. if the external frequency (v extclk/mode ) is greater than the internal oscillator frequency f osc , current is sourced continuously, pulling up the plllpf pin. when the exter- nal frequency is less than f osc , current is sunk continu- ously, pulling down the plllpf pin. if the external and internal frequencies are the same but exhibit a phase dif- ference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the plllpf pin is adjusted until the phase and frequency of the external oscillators are identical. at the stable operat- ing point, the phase comparator output is high impedance and the filter capacitor c lp holds the voltage. the loop filter components c lp and r lp smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components r lp and c lp determine how fast the loop acquires lock. typically, r lp = 10k and c lp is 2200pf to 0.01 m f. when not synchronized to an external clock, the figure 7. relationship between oscillator frequency and voltage at plllpf pin plllpf pin voltage (v) 0 250 frequency (khz) 350 450 550 650 0.4 0.8 1.2 1.6 3701 f07 2.0 2.4 750 300 400 500 600 700 800 figure 5. line regulation of v ref and maximum output current figure 6. setting output voltage input voltage (v) 75 normalized voltage or current (%) 85 95 105 80 90 100 2.2 2.4 2.6 2.8 3701 f05 3.0 2.1 2.0 2.3 2.5 2.7 2.9 v ref maximum output current 1/2 ltc3701 v fb 100pf v out r2 r1 3701 f06 phase-locked loop and frequency synchronization the ltc3701 has a phase-locked loop comprised of an internal voltage-controlled oscillator and phase detector. this allows the turn-on of the external p-channel mosfet of controller 1 to be locked to the rising edge of an external frequency source. the turn-on of controller 2s external p-channel mosfet is thus 180 degrees out of phase to the external clock. the nominal frequency range of the volt- age-controlled oscillator is 280khz to 775khz. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external oscillator.
14 ltc3701 3701fa internal oscillator frequency may be set by applying a dc voltage to the plllpf pin. 550khz operation can be selected by floating the plllpf pin. the plllpf pin may be connected to voltages as high as v in . applicatio s i for atio wu uu figure 9. foldback current limiting + 1/2 ltc3701 v fb i th/run r2 d fb1 v out d fb2 3701 f09 r1 typically much larger than the dc supply current. in continuous mode, i gatechg = f ? q p . 3) i 2 r losses are calculated from the dc resistances of the mosfet, inductor and sense resistor. in continuous mode, the average output current flows through l but is chopped between the p-channel mosfet in series with r sense and the output diode. the mosfet r ds(on) plus r sense multiplied by duty cycle can be summed with the resistance of l to obtain i 2 r losses. 4) the output diode is a major source of power loss at high currents and is worse at high input voltages. the diode loss is calculated by multiplying the forward voltage times the load current times the diode duty cycle. 5) transition losses apply to the external mosfet and increase with higher operating frequencies and input voltages. transition losses can be estimated from: transition loss = 2 (v in ) 2 i o(max) c rss (f) other losses, including c in and c out esr dissipative losses and inductor core losses, generally account for less than 2% total additional loss. foldback current limiting as described in the output diode selection, the worst- case diode dissipation occurs with a short-circuited out- put when the diode conducts the current limit value almost continuously. to prevent excessive heating in the diode, foldback current limiting can be added to reduce the current in proportion to the severity of the fault. foldback current limiting is implemented by adding di- odes d fb1 and d fb2 between the output and the i th /run pin as shown in figure 9. in a hard short (v out = 0v), the current will be reduced to approximately 50% of the maximum output current. figure 8. phase-locked loop block diagram digital phase/ frequency detector oscillator 2.4v r lp c lp 3701 f08 plllpf external oscillator extclk/ mode 10k efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C (l1 + l2 + l3 + ) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, five main sources usually account for most of the losses in ltc3701 circuits: 1) ltc3701 dc bias current, 2) mosfet gate charge current, 3) i 2 r losses, 4) voltage drop of the output diode and 5) transition losses. 1) the v in (pin) current is the dc supply current, given in the electrical characteristics, that excludes mosfet driver currents. v in current results in a small loss that increases with v in . 2) mosfet gate charge current results from switching the gate capacitance of the power mosfet. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from pv in to ground. the resulting dq/dt is a current out of pv in , which is
15 ltc3701 3701fa applicatio s i for atio wu uu checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( d i load )(esr), where esr is the effective series resistance of cout . d i load also begins to charge or dis- charge c out , which generates a feedback error signal. the regulator loop then returns v out to its steady-state value. during this recovery time, v out can be monitored for over- shoot or ringing. opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the i th series r c -c c filter (see functional diagram) sets the dominant pole-zero loop compensation. the i th exter- nal components shown in the figure 1 circuit will provide an adequate starting point for most applications. the values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capaci- tors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1 m s to 10 m s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability. the gain of the loop will be increased by increasing r c , and the bandwidth of the loop will be increased by decreasing c c . the output voltage settling behavior is related to the stability of the closed- loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to application note 76. a second, more severe transient is caused by switching in loads with large (>1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(c load ). thus a 10 m f capacitor would require a 250 m s rise time, limiting the charging current to about 200ma. minimum on-time considerations minimum on-time, t on(min) , is the smallest amount of time that the ltc3701 is capable of turning the top mosfet on and then off. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. the minimum on-time for the ltc3701 is about 250ns. low duty cycle and high frequency applica- tions may approach this minimum on-time limit and care should be taken to ensure that: t v fv on min out in () < if the duty cycle falls below what can be accommodated by the minimum on-time, the ltc3701 will begin to skip cycles. the output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3701. these items are illustrated graphically in the layout diagram of figure 10. figure 11 illustrates the current waveforms present in the various branches of the 2-phase regulators. check the following in your layout: 1) are the sense resistors and p-channel mosfets for the two channels located within 1cm of each other with a common connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop.
16 ltc3701 3701fa applicatio s i for atio wu uu 2) are the signal and power grounds kept separate? the ltc3701 signal ground consists of the feedback resistor divider, the i th /run compensation network, and pin 4. the power ground consists of the (C) terminal of c in , the (C) terminals of c out1,2 , the anodes of the schottky diodes, and pin 13 of the ltc3701. the power ground traces should be kept short, direct, and wide. connect the anode of the schottky diodes directly to the input capacitor ground. 3) do the v fb pins connect directly to the feedback resistors? put the feedback resistors close to the v fb pins. the traces connecting the top feedback resistors to the corresponding output capacitor should to be kelvin traces. 4) are the sense C and sense + leads routed together with minimum pc trace spacing? the (optional) filter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor. 5) keep the switching nodes (sw1, sw2) and top gate nodes (pgate1, pgate2) away from small-signal nodes, especially the opposite channels voltage and current sensing feedback pins. all of these nodes have large and fast moving signals and therefore should be keep on the output side of the ltc3701 and occupy minimum pc trace area. design example as a design example for one channel, assume v in will be operating from a maximum of 4.2v down to a minimum of 2.7v. load current requirement is a maximum of 1.5a , but most of the time it will be in a standby mode requiring only 2ma. efficiency at both low and high load currents is important. burst mode operation at light loads is desired. output voltage is 2.5v. maximum duty cycle = v out + + ? ? ? ? = v vv d in min d () % 93 from figure 2, sf = 57%. r sf i sense out ===w 12 7 100 057 12 7 1 5 003 . . .. . in the application, a 0.03 w resistor is used. the plllpf pin will be left floating, so the ltc3701 will operate at its default frequency of 550khz. for continuous operation in burst mode, the required minimum inductor value is: l vv khz v vv vv h min = w ? ? ? ? + + ? ? ? ? =m 42 25 550 003 003 25 03 42 03 200 .. . . .. .. . for the selection of the external mosfet, the r ds(on) must be guaranteed at 2.5v since the ltc3701 has to work down to 2.7v. let?s assume that the mosfet dissipation is to be limited to p p = 250mw and its thermal resistance is 50 c/w. hence, the junction temperature at t a = 25 c will be 37.5 c and d p = 0.005 ? (37.5 C 25) = 0.0625. the required r ds(on) is then given by: r p dc i p ds on p out () . ? + () =w 2 1 011 d the p-channel mosfet requirement can be met by an si3443dv. the requirement for the schottky diode is the most strin- gent when v out = 0v, i.e., short circuit. with a 0.03 w r sense resistor, the short-circuit current through the schottky is 0.1/0.03 = 3.3a. an mbrs340t3 schottky diode is chosen. with 3.3a flowing through, the diode is rated with a forward voltage of 0.4v. therefore, the worst- case power dissipated by the diode is 1.32w. the addition of d fb1 and d fb2 (figure 6) will reduce the diode dissipa- tion to approximately 0.66w the input capacitor requires an rms current rating of at least 0.75a at temperature, and c out will require an esr of 0.1 w for optimum efficiency.
17 ltc3701 3701fa 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 3701 f10 + + + sense1 i th /run1 v fb1 sgnd v fb2 i th /run2 plllpf sense2 sense1 + v in pgate1 pgnd pgate2 pgood extclk/mode sense2 + ltc3701 c out1 c in v out1 r sense1 r sense2 v in m1 l1 d1 + c out2 v out2 m2 l2 d2 + bold lines indicate high current paths r l1 d1 l1 sw1 r sense1 v out1 c out1 + v in c in r in + r l2 d2 bold lines indicate high, switching current lines. keep lines to a minimum length. l2 sw2 3701 f11 r sense2 v out2 c out2 + applicatio s i for atio wu uu figure 10. ltc3701 layout diagram figure 11. branch current waveforms
18 ltc3701 3701fa typical applicatio s u 2-phase, synchronizable dual output step-down dc/dc converter + lt1004-1 1.2v 15k 3 2 1 5 0.01 f fb2 3701 ta05 1n4148 4 v out1 lt1797 v in optional output sequencing circuit + + sense1 i th /run1 v fb1 sgnd v fb2 i th /run2 plllpf sense2 sense1 + v in pgate1 pgnd pgate2 pgood extclk/mode sense2 + 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc3701 c6 220pf c4 220pf r10 10k r5 10k 10k 10nf r6 78.7k r8 80k r9 100k r7 169k r1 0.03 l1 4.7 h c1 47 f c2 10 f c5 47 f c1, c5: sanyo 6tpa47m c2: taiyo yuden lmk325bj106k-t r2 0.03 l2 4.7 h d1 m1 m2 100k d2 v in 3701 ta02 v in 2.7v to 9.8v v out1 2.5v 2a gnd v out2 1.8v 2a d1, d2: ir10bq015 l1, l2: murata lqn6c-4r7 m1, m2: si3443dv r1, r2: dale 0.25w 2-phase, 550khz single output step-down dc/dc converter + sense1 i th /run1 v fb1 sgnd v fb2 i th /run2 plllpf sense2 sense1 + v in pgate1 pgnd pgate2 pgood extclk/mode sense2 + 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc3701 c4 220pf r5 10k r6 78.7k r7 169k r1 0.03 l1 4.7 h c1 47 f c2 10 f v in 2.5v to 9.8v v out 2.5v 4a r2 0.03 l2 4.7 h d1 m1 m2 d2 3701 ta03 c1: sanyo 6tpa47m c2: taiyo yuden lmk325bj106k-t d1, d2: ir10bq015 l1, l2: murata lqn6c-4r7 m1, m2: si3443dv r1, r2: dale 0.25w single cell li-ion to 3.3v (zeta converter) and 1.8v (buck converter) + + sense1 v fb1 i th /run1 sgnd i th /run2 v fb2 plllpf sense2 sense1 + v in pgate1 pgnd pgate2 pgood extclk/mode sense2 + 1 3 2 4 6 5 7 8 16 15 14 13 12 11 10 9 ltc3701 c6 470pf c4 220pf c3 10 f r10 47k r5 10k 10k 10nf r6 78.7k r8 80.6k r9 100k r7 249k r1 0.025 l1a l1b c1 c2 22 f c5 47 f c1, c5: sanyo 6tpa47m c2: taiyo yuden jmk325bj226mm c3: taiyo yuden jmk316bj106ml d1, d2: ir10bq015 r2 0.03 l2 4.7 h m1 m2 100k d2 d1 v in 3701 ta06 v in 2.7v to 4.2v v out1 3.3v 1a gnd v out2 1.8v 2a l1a, l1b: coiltronics ctx5-2 l2: murata lqn6c-4r7 m1, m2: si3443dv r1, r2: dale 0.25w
19 ltc3701 3701fa gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale typical applicatio s u + + sense1 i th /run1 v fb1 sgnd v fb2 i th /run2 plllpf sense2 sense1 + v in pgate1 pgnd pgate2 pgood extclk/mode sense2 + 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc3701 c6 220pf c4 220pf r10 10k r5 10k 10k 10nf r6 78.7k r8 80k r9 100k r7 169k r1 0.012 l1 1.5 h c1 47 f c2 10 f c5 47 f c1, c5: sanyo 6tpa47m c2: taiyo yuden lmk325bj106k-t r2 0.015 l2 1.5 h d1 m1 m2 100k d2 v in 3701 ta02 v in 2.7v to 9.8v v out1 2.5v 4a gnd v out2 1.8v 4a d1, d2: ir30bq015 l1, l2: coilcraft do3316p-152 m1, m2: si9803dy r1, r2: dale 0.25w 1nf 1nf 1 f 10 2-phase, synchronizable dual output step-down dc/dc converter with 4a output currents u package descriptio gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 ltc3701 3701fa part number description comments ltc1622 synchronizable low input voltage current mode v in 2v to 10v, burst mode operation, 8-lead msop step-down dc/dc controller ltc1628/ dual high efficiency, 2-phase synchronous constant frequency, standby, 5v and 3.3v ldos, v in to 36v, ltc1628-pg step down controllers 28-lead ssop ltc1629/ 20a to 200a polyphase tm high efficiency controllers expandable up to 12 phases, no heat sinks, v in to 36v, ltc1629-pg 28-lead ssop ltc1702a no r sense tm 2-phase dual synchronous controller 550khz, no sense resistor, gn24, v in to 7v ltc1708-pg dual high efficiency, 2-phase synchronous 1.3v v out 3.5v, current mode, 3.5v v in 36v step-down switching regulators ltc1735 high efficiency synchronous step-down controller burst mode operation, 16-pin narrow ssop, fault protection, 3.5v v in 36v ltc1767 1.2a i out , 1.25mhz, high efficiency step-down dc/dc converter 90% efficiency, v in : 3v to 25v, v out = 1.2v, i q = 1ma, i sd = 6 m a, ms8e package ltc1772 constant frequency current mode step-down 2.5v v in 9.8v, i out up to 4a, sot-23 package, 550khz dc/dc controller ltc1773 synchronous step-down controller 2.65v v in 8.5v, i out up to 4a, 10-lead msop ltc1778 no r sense synchronous step-down controller current mode operation without sense resistor, fast transient response, 4v v in 36v ltc1872 constant frequency current mode step-up controller 2.5v v in 9.8v, sot-23 package, 550khz ltc1929 constant frequency current mode 2-phase up to 42a, no heat sink, 3.5v v in 36v synchronous controller ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out = 0.8v, i q = 60 m a, i sd = <1 m a, ms package ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out = 0.8v, i q = 60 m a, i sd = <1 m a, tssop-16e package ltc3700 constant frequency step-down controller with ldo regulator 2.65 v in 9.8v, 550khz, 10-lead ssop ltc3728/ltc3728l dual, 550khz, 2-phase synchronous step-down constant frequency, v in to 36v, 5v and 3.3v ldos, switching regulator 5mm 5mm qfn or 28-lead ssop polyphase and no r sense are trademarks of linear technology corporation. ? linear technology corporation 2002 lt/tp 0403 1k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com typical applicatio u related parts dual input voltage single output, 2-phase, 550khz, step-down dc/dc converter + sense1 i th /run1 v fb1 sgnd v fb2 i th /run2 plllpf sense2 sense1 + v in pgate1 pgnd pgate2 pgood extclk/mode sense2 + 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc3701 c5 220pf r8 10k r6 78.7k r7 169k r1 0.03 l1 4.7 h c1 47 f c2 10 f r2 0.03 l2 4.7 h d1 m1 m2 d2 v in2 2.5v to 9.8v v in1 2.5v to 9.8v v in1 3 v in2 v out 2.5v 2a 3701 ta04 c3 10 f c1: sanyo 6tpa47m c2, c3: taiyo yuden lmk325bj106k-t d1, d2: ir10bq015 l1, l2: murata lqn6c-4r7 m1, m2: si3443dv r1, r2: dale 0.25w

▲Up To Search▲

Price & Availability of LTC3701EGN

	To Download LTC3701EGN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .